1. Technical Field of the Invention
The present invention relates generally to mixed signal circuitry and more particularly to providing a clock, which has a rising or falling edge during low noise periods, to jitter sensitive circuits.
2. Description of Related Art
FIG. 1 is a diagram of a buffer and corresponding ideal and actual signaling waveforms. As shown, the buffer has an input that receives a clock input signal and a corresponding output that produces a clock output signal. In an ideal signaling situation, the clock signal input transitions from a logic 0 to a logic 1 instantaneously (i.e., has zero transition times). The clock output signal also includes zero transition time for the ideal signaling but delayed slightly due to propagation delay of the buffer.
As is generally know in the art, digital circuitry, analog circuitry and mixed signal circuitry, especially when implemented on an integrated circuit do not exhibit ideal signaling. In practice, such circuits have a measurable transition time between logic 1 states and logic 0 states. In addition, as shown in the actual signaling, due to the non-zero transition times, and the imperfections of the components comprising the circuitry, jitter results in the signal. As is known, jitter sensitivity to a clock signal limits the ability of circuitry that utilizes the clock signal to accurately perform its function. As is further known, as the speed of signal processing increases, jitter and control thereof becomes an increasing challenge.
To date many approaches have been utilized to reduce jitter including decreasing rise and fall times of signals, improving stability of voltage levels, tightening input thresholds for logic devices, reducing sensitivity of input thresholds due to logic voltage variations, utilizing differential signaling, and isolation of critical logic elements from neighboring noise generating elements. While each of these techniques improves performance by reducing jitter, the jitter is not fully eliminated.
As the demand for higher data rates continues, further reduction in jitter is needed. Therefore, a need exists for a method and apparatus of a clock and clock adjustment circuit for minimum jitter.